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| the m pd75p068 is produced by replacing the internal mask rom of the m pd75068 with a one-time prom in which data can be written once. the following user's manual describes the details of the functions of the m pd75p068. be sure to read it before designing an application system. m pd75068 user's manual: ieu-1366 features ? compatible with the m pd75068 ? can be replaced with the m pd75068 containing mask rom on a full-production basis. ? internal one-time prom: 8064 words 8 bits ? internal ram: 512 words 4 bits ? internal pull-up resistors can be specified with software: ports 0 to 3 and 6 ? n-ch open-drain input-output: ports 4 and 5 ? can operate at low voltage: v dd = 2.7 to 6.0 v ordering information part number package quality grade m pd75p068cu 42-pin plastic shrink dip (600 mil) standard m pd75p068gb-3b4 44-pin plastic qfp (square 10 mm) standard caution the m pd75p068 is not provided with mask-selected pull-up resistors. please refer to "quality grades on nec semiconductor devices" (document number iei-1209) published by nec corporation to know the specification of quality grade on the devices and its recommended applications. data sheet mos integrated circuit m pd75p068 document no. ic-3290a (o.d. no. ic-8623a date published april 1994 p printed in japan 4 bit single-chip microcomputer 1990 the information in this document is subject to change without notice. major changes in this revision are indicated by stars ( h ) in the margins. nec corporation 1993
2 m pd75p068 pin configuration (top view) ? 42-pin plastic shrink dip ? 44-pin plastic qfp int2/p12 int1/p11 int0/p10 sb1/si/p03 sb0/so/p02 sck /p01 int4/p00 p53 p52 p51 p50 p112 /an2 p113/an3 p60/kr0/an4 p61/kr1/an5 p62/kr2/an6 p63/kr3/an7 av ss p30/md0 p31/md1 p32/md2 p33/md3 p13/ ti0 p20/pto0 p21 p22/pcl p23/buz v dd v pp av ref p110/an0 p111/an1 nc nc p43 p42 p41 p40 v ss xt1 xt2 reset x1 x2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 33 32 31 30 29 28 27 26 25 24 23 44 43 42 41 40 39 38 37 36 35 34 pd75p068gb-3b4 m xt1 xt2 reset x1 x2 md3/p33 md2/p32 md1/p31 md0/p30 av ss an7/kr3/p63 an6/kr2/p62 an5/kr1/p61 an4/kr0/p60 an3/p113 an2/p112 an1/p111 an0/p110 av ref v pp v dd v ss p40 p41 p42 p43 p50 p51 p52 p53 p00/int4 p01/sck p02/so/sb0 p03/si/sb1 p10/int0 p11/int1 p12/int2 p13/ ti0 p20/pto0 p21 p22/pcl p23/buz 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 pd75p068cu m 3 m pd75p068 block diagram port 0 bit sequential buffer port 1 port 2 port 3 port 4 port 5 port 6 port 11 p10-p13 p20-p23 p30/md0-p33/md3 p40-p43 p50-p53 p60-p63 p110-p113 sp alu bank general register ram data memory decode and control prom program memory clock output control clock divider clock generator f x /2 n main stand by control cpu clock f program counter (13) basic interval timer cy intbt intt0 ti0/p13 pto0/p20 si/sb1/p03 so/sb0/p02 sck/p01 timer/ counter #0 serial interface intcsi int0/p10 int1/p11 int2/p12 int4/p00 kr0-kr3/p60-p63 interrupt control buz/p23 watch timer intw a/d converter an0-an3/p110-p113 an4-an7/p60-p63 av ref av ss v pp pcl/p22 sub xt1 xt2 x1 x2 v dd v ss reset p00-p03 8064 8 bits 512 4 bits 4 4 4 4 4 4 4 4 4 8 4 m pd75p068 contents 1. pin functions ........................................................................................................................ 5 1.1 port pins .......................................................................................................................................... 5 1.2 non-port pins ................................................................................................................................ 6 1.3 pin input/output circuits ........................................................................................................ 7 2. difference between the m pd75p068 and m pd75068 ................................................... 9 3. writing to and verifying prom (program memory) ............................................ 10 3.1 operating modes when writing to and verifying the program memory ......... 10 3.2 writing to the program memory ......................................................................................... 11 3.3 reading the program memory .............................................................................................. 12 4. screening one-time prom products ........................................................................... 13 5. electrical characteristics ............................................................................................. 14 6. characteristic curves (for reference) ..................................................................... 27 7. package drawings .............................................................................................................. 33 8. recommended soldering conditions ....................................................................... 35 appendix a development tools .......................................................................................... 36 appendix b related documents .......................................................................................... 37 h h h 5 m pd75p068 function 4-bit input port (port0). for p01-p03, pull-up resistors can be provided by software in units of 3 bits. with noise elimination function 4-bit input port (port1). pull-up resistors can be provided by software in units of 4 bits. 4-bit i/o port (port2). pull-up resistors can be provided by software in units of 4 bits. programmable 4-bit i/o port (port3). i/o can be specified bit by bit. pull-up resistors can be provided by software in units of 4 bits. n-ch open-drain 4-bit i/o port (port4). withstand voltage of 10 v data input-output (low-order 4 bits) when writing to and verifying program memory (prom) n-ch open-drain 4-bit i/o port (port5). withstand voltage of 10 v data input-output (high-order 4 bits) when writing to and verifying program memory (prom) programmable 4-bit i/o port (port6). pull-up resistors can be provided by software in units of 4 bits. 4-bit input port (port11) 1. pin functions 1.1 port pins when reset input input input input high impedance high impedance input input 8 bit i/o l l shared pin int4 sck so/sb0 si/sb1 int0 int1 int2 ti0 pto0 pcl buz md0 md1 md2 md3 kr0/an4 kr1/an5 kr2/an6 kr3/an7 an0 an1 an2 an3 pin p00 p01 p02 p03 p10 p11 p12 p13 p20 p21 p22 p23 p30 note 2 p31 note 2 p32 note 2 p33 note 2 p40-p43 note 2 p50-p53 note 2 p60 p61 p62 p63 p110 p111 p112 p113 input/ output input i/o i/o i/o input i/o i/o i/o i/o i/o input b f-a f-b m-c b-c e-b e-b m-a m-a y-d y-a i/o circuit type note 1 notes 1. the circle ( l l ) indicates the schmitt trigger input. 2. can directly drive the led. 6 m pd75p068 function input for receiving external event pulse signal for timer/event counter timer/event counter output clock output output for arbitrary frequency output (for buzzer output or system clock trimming) serial clock i/o serial data output serial bus i/o serial data input serial bus i/o edge detection vectored interrupt input (either rising edge or falling edge detection) edge detection vectored interrupt input (detection edge selectable) edge detection testable input (rising edge detection) parallel falling edge detection testable input for a/d converter only crystal/ceramic connection for main system clock generation. when external clock signal is used, it is applied to x1, and its reverse phase signal is applied to x2. crystal connection for subsystem clock generation. when external clock signal is used, it is applied to xt1, and its reverse phase signal is applied to xt2. xt1 can be used as a 1-bit input (test). system reset input mode selection when writing to or verifying program memory (prom) programming voltage application when writing to or verifying program memory (prom) directly connected to v dd during normal operation. +12.5 v is applied when data is written in prom or when the prom is verified. main power supply gnd potential pin ti0 pto0 pcl buz sck so/sb0 si/sb1 int4 int0 int1 int2 kr0-kr3 an0-an3 an4-an7 av ref av ss x1, x2 xt1, xt2 reset md0-md3 v pp note 2 v dd v ss shared pin p13 p20 p22 p23 p01 p02 p03 p00 p10 p11 p12 p60-p63/ an4-an7 p110-p113 p60-p63/ kr0-kr3 p30-p33 when reset input input input input input input input input input input input input b -c e-b e-b e-b f-a f-b m-c b b-c b-c y-d y-a y-d z z b e-b i/o circuit type note 1 8-bit analog input reference voltage input gnd potential input/ output input i/o i/o i/o i/o i/o i/o input input input i/o input i/o input input input input i/o notes 1. the circle ( l l ) indicates the schmitt trigger input. 2. unless the v pp pin is directly connected to the v dd pin during normal operation, the m pd75p068 does not operate normally. 1.2 non-port pins 7 m pd75p068 (1/3) type a (for type e-b) v dd p-ch in n-ch cmos input buffer output disable data v dd p-ch out n-ch in schmitt trigger input with hysteresis push-pull output which can be set to high-impedance output (off for both p-ch and n-ch) v dd p-ch p.u.r.: pull-up resistor in/out p.u.r. enable type d type a dd v p.u.r. p.u.r. enable p-ch in p.u.r.: pull-up resistor type b type e-b output disable data type b-c p.u.r. type d (for type e-b,f-a) 1.3 pin input/output circuits the input/output circuit of each m pd75p068 pin is shown below in a simplified manner. 8 m pd75p068 (2/3) data type f-b type f-a type m-a type y (for type y-a , y-d) type m-c type y-a data output disable p-ch p.u.r.: pull-up resistor in/out p.u.r. enable type d type b v dd p.u.r. data p.u.r.: pull-up resistor n-ch p.u.r. enable in/out p-ch v dd p.u.r. p.u.r. enable p-ch in v dd p.u.r v dd p-ch n-ch p.u.r.: pull-up resistor (p) p-ch n-ch v dd output disable output disable output disable output disable (n) input enable sam- pling c av ss v dd reference voltage (from voltage tap of serial resistor string) in/out in/out n-ch (withstand voltage: +10 v) output disable data p.u.r.: pull-up resistor input buffer with an intermediate withstand voltage of +10 v av ss + type y type a in instruction input buffer in h 9 m pd75p068 ? 0000h to 1f7fh ? 8064 words 8 bits can be specified with software. 2.7 to 6.0 v (3/3) type y-d data output disable p-ch p.u.r.: pull-up resistor in/out p.u.r. enable type d type b v dd p.u.r. type z reference voltage av ref av ss type y m pd75p068 (mask rom product) item program memory pull-up resistor xt1 feedback resistor operating supply voltage range pin function electrical characteristics others m pd75p068 (one-time prom product) they differ in consumption current. for details, refer to the corresponding items in each data sheet. since they differ in circuit scale and mask layout, they differ in noise immu- nity and noise radiation. none contained p30/md0 to p33/md3 v pp mask option mask option p30 to p33 ic 2. difference between the m pd75p068 and m pd75068 the m pd75p068 is produced by replacing the internal mask rom (program memory) of the m pd75068 with a one-time prom in which data can be written once. both have the same cpu function and internal hardware. table 2-1 shows the difference between the m pd75p068 and m pd75068. for details of the cpu function and internal hardware, refer to the individual references for the m pd75068. table 2-1 difference between the m pd75p068 and m pd75068 caution the prom and mask rom products differ in noise immunity and noise radiation. use not es products but cs products (mask rom products) to evaluate them thoroughly when considering the change from the prom products to the mask rom products during processes from preproduction to volume production. ports 0 to 3 and 6 ports 4 and 5 pins 6 to 9 of sdip pins 23 to 26 of qfp pin 20 of sdip pin 38 of qfp 10 m pd75p068 function voltage is applied to this pin when writing to the program memory or verifying its contents (normally v dd electric potential). address update clock inputs used when writing to the program memory or verifying its contents. the x2 pin is used to input the inverted signal of the x1 pin input. operation mode selection pins used when writing to the program memory or verifying its contents. i/o pins for 8-bit data used when writing to the program memory or verifying its contents. power voltage is applied to this pin. during normal operation, 2.7 to 6.0 v should be applied; 6 v should be applied when writing to the program memory or verifying its contents. pin name v pp x1, x2 md0 to md3 (p30 to p33) p40 to p43 (low-order four bits) p50 to p53 (high-order four bits) v dd v dd +6 v md0 h l l h md1 l h l md2 h h h h md3 l h h h program memory address clear mode write mode verify mode program inhibit mode v pp +12.5 v operating mode specification operating mode indicates l or h. 3. writing to and verifying prom (program memory) the program memory in the m pd75p068 is a one-time prom which consists of 8064 words 8 bits. writing to and verifying the contents of the one-time prom is accomplished using the pins shown in the table below. note that address inputs are not used; instead, the address is updated using the clock input from the x1 pin. caution since the m pd75p068cu/gb does not have an erasure window, the contents of the memory can not be erased with ultraviolet radiation. 3.1 operating modes when writing to and verifying the program memory if +6 v is applied to the v dd pin and +12.5 v is applied to the v pp pin, the m pd75p068 enters program memory write/verify mode. the specific operating mode is then selected by setting the md0 through md3 pins as listed below. the remaining pins are all connected to v ss via pull-down resistors. 11 m pd75p068 v pp v dd v pp v dd +1 v dd v dd x1 p40-p43 p50-p53 md0 (p30) md1 (p31) md2 (p32) md3 (p33) data input data output data input write verify additional write address increment repeat x times 3.2 writing to the program memory the procedure for writing to program memory is described below; high-speed write is possible. (1) connect all unused pins to v ss through resistors. apply a low-level signal to the x1 pin. (2) apply 5 v to v dd and v pp pins. (3) wait 10 m s. (4) select program memory address clear mode. (5) apply +6 v to v dd and +12.5 v to v pp . (6) select program inhibit mode. (7) select write mode for 1 ms duration and write data. (8) select program inhibit mode. (9) select verify mode. if write is successful, proceed to step (10). if write fails, repeat steps (7) to (9). (10) perform additional write for (number (x) of repetitions of steps (7) to (9)) 1 ms duration. (11) select program inhibit mode. (12) increment the program memory address by inputting four pulses on the x1 pin. (13) repeat steps (7) to (12) until the last address is reached. (14) select program memory address clear mode. (15) apply 5 v to v dd and v pp pins. (16) turn the power off. the timing for steps (2) to (12) is shown below. 12 m pd75p068 v pp v dd v pp v dd +1 v dd v dd x1 p40-p43 p50-p53 md0 (p30) md1 (p31) md2 (p32) md3 (p33) data output data output ? 3.3 reading the program memory the procedure for reading the contents of program memory is described below. the read is performed in the verify mode. (1) connect all unused pins to v ss through resistors. apply a low-level signal to the x1 pin. (2) apply 5 v to v dd and v pp pins. (3) wait 10 m s. (4) select program memory address clear mode. (5) apply +6 v to v dd and +12.5 v to v pp . (6) select program inhibit mode. (7) select verify mode. data is output sequentially one address at a time for each cycle of four clock pulses appearing on the x1 pin. (8) select program inhibit mode. (9) select program memory address clear mode. (10) apply 5 v to v dd and v pp pins. (11) turn the power off. the timing for steps (2) to (9) is shown below. 13 m pd75p068 4. screening one-time prom products nec cannot execute a complete test of one-time prom products ( m pd75p068cu and m pd75p068gb-3b4) due to their structure before shipment. it is recommended that you screen (verify) prom products after writing necessary data into them and storing them at 125 c for 24 hours. nec offers a charged service called qtop microcomputer service. this service includes writing to one- time prom, marking, screening, and verification. ask your sales representative for details. h 14 m pd75p068 parameter supply voltage supply voltage input voltage output voltage high-level output current low-level output current operating temperature storage tempera- ture unit v v v v v ma ma ma ma ma ma ma ma ma ma ?c ?c symbol v dd v pp v i1 v i2 v o i oh i ol note t opt t stg conditions rated value C0.3 to +7.0 C0.3 to +13.5 C0.3 to v dd + 0.3 C0.3 to +11 C0.3 to v dd + 0.3 C10 C30 30 15 20 5 160 120 30 20 C40 to +85 C65 to +150 ports 4 and 5 n-ch open drain peak value rms peak value rms peak value rms peak value rms ports other than ports 4 and 5 1 pin all pins 1 pin of ports 0, 3, 4, and 5 1 pin of ports 2 and 6 total of all pins of ports 0, 3, 4, and 5 total of all pins of ports 2, and 6 5. electrical characteristics absolute maximum ratings (t a = 25 c) note calculate rms with [rms] = [peak value] ? duty. caution absolute maximum ratings are rated values beyond which some physical damages may be caused to the product; if any of the parameters in the table above exceeds its rated value even for a moment, the quality of the product may deteriorate. be sure to use the product within the rated values. input capacitance output capacitance i/o capacitance c i c o c io symbol parameter 15 15 15 pf pf pf unit max. typ. min. f = 1 mhz 0 v for pins other than pins to be measured conditions capacitance (t a = 25 c, v dd = 0 v) 15 m pd75p068 characteristics of the main system clock oscillator (t a = -40 to +85 c, v dd = 2.7 to 6.0 v) notes 1. the oscillator frequency and input frequency indicate only the oscillator characteristics. see the item of ac characteristics for the instruction execution time. 2. the oscillation settling time means the time required for the oscillation to settle after v dd is reaches the minimum voltage in the oscillation voltage range. 3. when 4.19 mhz < f x 5.0 mhz, do not select pcc = 0011 as the instruction execution time. when pcc = 0011, one machine cycle falls short of 0.95 m s, the minimum value for the standard. caution when the main system clock oscillator is used, conform to the following guidelines when wiring at the portions surrounded by dotted lines in the figures above to eliminate the influence of the wiring capacity. ? the wiring must be as short as possible. ? other signal lines must not run in these areas. ? any line carrying a high fluctuating current must be kept away as far as possible. ? the grounding point of the capacitor of the oscillator must have the same potential as that of v dd . it must not be grounded to ground patterns carrying a large current. ? no signal must be taken from the oscillator. recommended constant ceramic resonator crystal external clock oscillator frequency (f x ) note 1 oscillation settling time note 2 oscillator frequency (f x ) note 1 oscillation settling time note 2 x1 input frequency (f x ) note 1 x1 input high/low level width (t xh , t xl ) resonator parameter mhz ms mhz ms ms mhz ns 4.19 min. typ. max. unit conditions 1.0 1.0 1.0 100 v dd = 4.5 to 6.0 v 5.0 note 3 4 5.0 note 3 10 30 5.0 note 3 500 x1 x2 m pd74hcu04 x1 x2 v ss c1 c2 x1 x2 v ss c1 c2 16 m pd75p068 characteristics of the subsystem clock oscillator (t a = -40 to +85 c, v dd = 2.7 to 6.0 v) notes 1. the oscillator frequency and input frequency indicate only the oscillator characteristics. see the item of ac characteristics for the instruction execution time. 2. the oscillation settling time means the time required for the oscillation to settle after v dd reaches the minimum voltage in the oscillation voltage range. caution when the subsystem clock oscillator is used, conform to the following guidelines when wiring at the portions surrounded by dotted lines in the figures above to eliminate the influence of the wiring capacity. ? the wiring must be as short as possible. ? other signal lines must not run in these areas. ? any line carrying a high fluctuating current must be kept away as far as possible. ? the grounding point of the capacitor of the oscillator must have the same potential as that of v ss . it must not be grounded to ground patterns carrying a large current. ? no signal must be taken from the oscillator. when the subsystem clock is used, pay special attention to its wiring; the subsystem clock oscillator has low amplification to minimize current consumption and is more likely to malfunc- tion due to noise than the main system clock oscillator. recommended constant oscillator frequency (f xt ) note 1 oscillation settling time note 2 xt1 input frequency (f xt ) note 1 xt1 input high/low level width (t xth , t xtl ) crystal external clock resonator parameter khz s s khz m s 32.768 1.0 32 32 5 35 2 10 100 15 min. typ. max. unit conditions v dd = 4.5 to 6.0 v xt1 xt2 xt1 xt2 v ss c4 r c3 17 m pd75p068 3.58 4.00 5.00 4.19 frequency (mhz) recommended capacitors in the oscillation circuit recommended constant oscillation voltage range c1 (pf) c2 (pf) min. (v) max. (v) 1.00 3.00 kbr-1000f/y kbr-2.0ms pbrc 2.00a kbr-3.0ms kbr-3.58msa pbrc 3.58a kbr-3.58mks kbr-3.58mws kbr-4.00msa pbrc 4.00a kbr-4.00mks kbr-4.00mws kbr-5.0msa pbrc 5.00a kbr-5.0mks kbr-5.0mws crhf2.50 crhf4.19 crht4.19 crhf5.00 kyocera 2.50 5.00 150 150 2.00 47 47 33 33 33 33 contained contained contained contained 33 33 contained contained 30 30 contained contained 30 30 2.7 6.0 2.7 6.0 manufacturer part number main system clock: ceramic resonator (t a = C20 to +80 c) frequency (mhz) recommended constant oscillation voltage range c1 (pf) c2 (pf) min. (v) max. (v) manufacturer part number main system clock: crystal (t a = C40 to +85 c) kinseki 22 22 3.5 6.0 2.00 4.19 6.00 hc-49/u recommended constant oscillation voltage range max. (v) manufacturer part number subsystem clock: crystal (t a = C15 to +60 c) 32.768 15 27 220 2.7 6.0 kyocera kf-38g frequency (khz) min. (v) r (k w ) c4 (pf) h toko c3 (pf) 18 m pd75p068 dc characteristics (t a = -40 to +85 c, v dd = 2.7 to 6.0 v) ports 4 and 5 port 3 v dd = 4.5 to 6.0 v, i ol = 1.6 ma i ol = 400 m a sb0 and sb1 v i = v dd v i = 10 v v i = 0 v v o = v dd v o = 10 v v o = 0 v symbol v ih1 v ih2 v ih3 v ih4 v il1 v il2 v il3 v oh v ol i lih1 i lih2 i lih3 i lil1 i lil2 i loh1 i loh2 i lol r u ports 2, 3, and 11 ports 0, 1, and 6, and reset ports 4 and 5 x1, x2, xt1, and xt2 ports 2 to 5 and 11 ports 0, 1, and 6, and reset x1, x2, xt1, and xt2 v dd = 4.5 to 6.0 v, i oh = C1 ma i oh = C100 m a i dd1 i dd2 i dd3 i dd4 i dd5 v dd = 5.0 v 10 % note 3 v dd = 3.0 v 10 % note 4 halt mode v dd = 5.0 v 10 % v dd = 3.0 v 10 % v dd = 3.0 v 10 % halt mode v dd = 3.0 v 10 % v dd = 5.0 v 10 % v dd = 3.0 v 10 % t a = 25 ?c power supply current note 1 conditions parameter high-level input voltage low-level input voltage high-level output voltage low-level output voltage high-level input leakage current low-level input leakage current high-level output leakage current low-level out-put leakage current built-in pull-up resistor min. 0.7v dd 0.8v dd 0.7v dd v dd C 0.5 0 0 0 v dd C 1.0 v dd C 0.5 15 30 typ. 0.7 0.8 40 3.3 0.45 600 220 35 5 0.5 0.1 0.1 max. v dd v dd 10 v dd 0.3v dd 0.2v dd 0.4 2.0 2.0 0.4 0.5 0.2v dd 3 20 20 C3 C20 3 20 C3 80 300 10 1.4 1800 700 120 15 20 10 5 unit v v v v v v v v v v v v v v m a m a m a m a m a m a m a m a k w k w ma ma m a m a m a m a m a m a m a p01, p02, p03, and ports 1 to 3, and 6 v i = 0 v v dd = 4.5 to 6.0 v, i ol = 15 ma v dd = 4.5 to 6.0 v, i ol = 15 ma pull-up resistor: 1 k w or more other than x1, x2, xt1, and xt2 x1, x2, xt1, and xt2 ports 4 and 5 other than x1, x2, xt1, and xt2 x1, x2, xt1, and xt2 ports 4 and 5 v dd = 5.0 v 10 % v dd = 3.0 v 10 % notes 1. this current excludes the current which flows through the built-in pull-up resistors. 2. this value applies also when the subsystem clock oscillates. 3. value when the processor clock control register (pcc) is set to 0011 and the m pd75036 is operated in the high-speed mode 4. value when the pcc is set to 0000 and the m pd75036 is operated in the low-speed mode 5. this value applies when the system clock control register (scc) is set to 1001 to stop the main system clock pulse and to start the subsystem clock pulse. 4.19 mhz note 2 crystal resonance c1 = c2 = 22 pf 32.768 khz note 5 crystal resonance xt1 = 0 v 19 m pd75p068 conditions ac characteristics (t a = -40 to +85 c, v dd = 2.0 to 6.0 v) notes 1. the cycle time of the cpu clock ( f ) depends on the connected resonator frequency, the system clock control register (scc), and the processor clock control register (pcc). the figure on the right side shows the cycle time t cy characteristics for the supply voltage v dd during main sys- tem clock operation. 2. this value becomes 2t cy or 128/f x according to the setting of the inter- rupt mode register (im0). parameter symbol t cy f ti t tih , t til t inth , t intl t rsl cpu clock cycle time (minimum instruction execution time = 1 machine cycle) note 1 ti0 input frequency ti0 input high/low level width interrupt input high/ low level width reset low level width min. typ. max. unit 122 64 64 125 1 275 m s m s m s mhz khz m s m s m s m s m s m s 0.95 3.8 114 0 0 0.48 1.8 note 2 10 10 10 v dd = 4.5 to 6.0 v operated by main system clock pulse operated by subsystem clock pulse v dd = 4.5 to 6.0 v v dd = 4.5 to 6.0 v int0 int1, int2, and int4 kr0 to kr3 70 64 60 6 5 4 3 2 1 0.5 0123 456 operation guaranteed range t cy vs v dd (main system clock in operation) power supply voltage v dd [v] cycle time t cy [ s] m 20 m pd75p068 min. 1600 3800 t kcy1 /2 C 50 t kcy1 /2 C 150 150 400 0 0 symbol t kcy1 t kl1 t kh1 t sik1 t ksi1 t kso1 parameter sck cycle time sck high/low level width si setup time (referred to sck ) si hold time (referred to sck ) delay time from sck ? to so output r l = 1 k w, c l = 100 pf note v dd = 4.5 to 6.0 v typ. unit ns ns ns ns ns ns ns ns max. 250 1000 conditions v dd = 4.5 to 6.0 v v dd = 4.5 to 6.0 v symbol t kcy2 t kl2 t kh2 t sik2 t ksi2 t kso2 parameter sck cycle time sck high/low level width si setup time (referred to sck ) si hold time (referred to sck ) delay time from sck ? to so output min. 800 3200 400 1600 100 400 0 0 typ. max. 300 1000 unit ns ns ns ns ns ns ns ns conditions v dd = 4.5 to 6.0 v v dd = 4.5 to 6.0 v r l = 1 k w, c l = 100 pf note v dd = 4.5 to 6.0 v serial transfer operation two-wire and three-wire serial i/o modes (sck ... internal clock output): two-wire and three-wire serial i/o modes (sck ... external clock input): note r l and c l are the resistance and capacitance of the so output line load respectively. 21 m pd75p068 t kcy3 t kl3 t kh3 t sik3 t ksi3 t kso3 t ksb t sbk t sbl t sbh sbi mode (sck ... internal clock output (master)): sbi mode (sck ... external clock input (slave)): note r l and c l are the resistance and capacitance of the sb0/sb1 output line load respectively. 250 1000 1600 3800 t kcy3 /2 - 50 t kcy3 /2 - 150 150 t kcy3 /2 0 0 t kcy3 t kcy3 t kcy3 t kcy3 ns ns ns ns ns ns ns ns ns ns ns ns v dd = 4.5 to 6.0 v v dd = 4.5 to 6.0 v v dd = 4.5 to 6.0 v r l = 1 k w , c l = 100 pf note conditions parameter min. typ. max. unit sck cycle time sck high/low level width sb0/sb1 setup time (referred to sck - ) sb0/sb1 hold time (referred to sck - ) delay time from sck to sb0/sb1 output from sck - to sb0/sb1 from sb0/sb1 to sck sb0/sb1 low level width sb0/sb1 high level width symbol parameter t kcy4 t kl4 t kh4 t sik4 t ksi4 t kso4 t ksb t sbk t sbl t sbh 300 1000 min. unit max. typ. conditions v dd = 4.5 to 6.0 v v dd = 4.5 to 6.0 v r l = 1 k w , c l = 100 pf note v dd = 4.5 to 6.0 v 800 3200 400 1600 100 t kcy4 /2 0 0 t kcy4 t kcy4 t kcy4 t kcy4 sck cycle time sck high/low level width sb0/sb1 setup time (referred to sck - ) sb0/sb1 hold time (referred to sck - ) delay time from sck to sb0/sb1 output from sck - to sb0/sb1 from sb0/sb1 to sck sb0/sb1 low level width sb0/sb1 high level width symbol ns ns ns ns ns ns ns ns ns ns ns ns 22 m pd75p068 a/d converter (t a = -40 to +85 c, v dd = 2.7 to 6.0 v, av ss = v ss = 0 v) notes 1. absolute accuracy excluding quantization error ( 1/2 lsb) 2. 2.5 v av ref v dd adm1 is set to 0 or 1 depending on the a/d converter reference voltage (av ref ) as follows: when 0.6v dd av ref 0.65v dd , adm1 can be set to either 0 or 1. 3. time from the execution of a conversion start instruction till the end of conversion (eoc = 1) (40.1 m s: f x = 4.19 mhz) 4. time from the execution of a conversion start instruction till the end of sampling ( 10.5 m s: f x = 4.19 mhz) resolution absolute accuracy note 1 conversion time note 3 sampling time note 4 reference input voltage analog input voltage analog input imped- ance av ref current symbol parameter t conv t samp av ref v ian r an ai ref -10 ta +85?c -40 ta < -10?c conditions 2.5 v av ref v dd note 2 8 2.5 av ss min. max. unit 8 1000 0.7 bit lsb lsb m s m s v v m w ma 8 1.5 2.0 168/f x 44/f x v dd av ref 2.0 typ. 2.5 v 0.6v dd 0.65v dd v dd (2.7 to 6.0 v) adm1 = 0 adm1 = 1 av ref 23 m pd75p068 ac timing measurement points (excluding x1 and xt1 inputs) c lock timing ti0 timing t xl t xh 1/f x x1 input v dd ?0.5 v 0.4 v t til t tih 1/f ti ti0 t xtl t xth 1/f xt xt1 input v dd ?0.5 v 0.4 v measurement points 0.2v dd 0.8v dd 0.2v dd 0.8v dd 24 m pd75p068 t kl1 t kcy1 t sik1 t kh1 t ksi1 t kso1 input data output data sck si so serial transfer timing three-wire serial i/o mode: two-wire serial i/o mode: t kcy2 t kl2 t kh2 t ksi2 t sik2 t kso2 sck sb0 and sb1 25 m pd75p068 serial transfer timing bus release signal transfer: command signal transfer: interrupt input timing reset input timing sck sb0 and sb1 t ksb t kl3 t kl4 t kcy3 t kcy4 t kso3 t kso4 t sbk t kh3 t kh4 t sik3 t sik4 t ksi3 t ksi4 sck sb0 and sb1 t ksb t sbl t sbh t sbk t kcy3 t kcy4 t kso3 t kso4 t kl3 t kl4 t kh3 t kh4 t ksi3 t ksi4 t sik3 t sik4 reset t rsl int0, int1, int2 and int4 kr0-kr3 t intl t inth 26 m pd75p068 parameter symbol data hold supply voltage data hold supply current note 1 release signal setting time oscillation settling time note 2 v dddr i dddr t srel t wait min. typ. max. unit 2.0 0 0.1 2 17 /f x note 3 6.0 10 v m a m s ms ms v dddr = 2.0 v release by reset release by interrupt request conditions data hold characteristics by low supply voltage in data memory stop mode (t a = -40 to +85 c) notes 1. excluding the current which flows through the built-in pull-up resistors 2. cpu operation stop time for preventing unstable operation at the beginning of oscillation 3. this value depends on the settings of the basic interval timer mode register (btm) shown below. data hold timing (stop mode release by reset) data hold timing (standby release signal: stop mode release by interrupt signal) 0 1 0 1 0 1 1 1 btm0 btm1 0 0 1 1 btm2 btm3 2 20 /f x (approx. 250 ms) 2 17 /f x (approx. 31.3 ms) 2 15 /f x (approx. 7.82 ms) 2 13 /f x (approx. 1.95 ms) wait time (values at f x = 4.19 mhz in parentheses) reset v dd v dddr t srel t wait internal reset operation halt mode operation mode stop instruction execution data hold mode stop mode standby release signal (interrupt request) v dd v dddr t srel t wait halt mode operation mode stop instruction execution data hold mode stop mode 27 m pd75p068 6. characteristic curves (for reference) i dd vs v dd (when the main system clock operates at 4.19 mhz with a crystal) h main system clock stop mode + 32 khz oscillation, and subsystem clock halt mode subsystem clock operating mode main system clock halt mode + 32 khz oscillation (t a = 25 ?c) x1 x2 xt1 xt2 22 pf 330 k w crystal 4.19 mhz 22 pf 18 pf 18 pf crystal 32.768 khz pcc = 0011 pcc = 0010 pcc = 0000 supply voltage v dd (v) 8 6 4 2 0 supply current i dd ( m a) 5.0 3.0 1.0 0.5 0.1 0.05 0.01 0.005 0.001 28 m pd75p068 i dd vs v dd (when the main system clock operates at 2.0 mhz with a crystal) main system clock stop mode + 32 khz oscillation, and subsystem clock halt mode subsystem clock operating mode main system clock halt mode + 32 khz oscillation (t a = 25 ?c) x1 x2 xt1 xt2 22 pf 330 k w crystal 2.0 mhz 22 pf 18 pf 18 pf crystal 32.768 khz pcc = 0011 pcc = 0010 pcc = 0000 supply voltage v dd (v) 8 6 4 2 0 supply current i dd ( m a) 5.0 3.0 1.0 0.5 0.1 0.05 0.01 0.005 0.001 29 m pd75p068 i dd vs v dd (when the main system clock operates at 4.19 mhz with a ceramic resonator) main system clock stop mode + 32 khz oscillation, and subsystem clock halt mode subsystem clock operating mode main system clock halt mode + 32 khz oscillation (t a = 25 ?c) x1 x2 xt1 xt2 30 pf 330 k w ceramic resonator 4.19 mhz 30 pf 18 pf 18 pf crystal 32.768 khz pcc = 0011 pcc = 0010 pcc = 0000 supply voltage v dd (v) 8 6 4 2 0 supply current i dd ( m a) 5.0 3.0 1.0 0.5 0.1 0.05 0.01 0.005 0.001 30 m pd75p068 i dd vs v dd (when the main system clock operates at 2.0 mhz with a ceramic resonator) main system clock stop mode + 32 khz oscillation, and subsystem clock halt mode subsystem clock operating mode main system clock halt mode + 32 khz oscillation (t a = 25 ?c) pcc = 0011 pcc = 0010 pcc = 0000 supply voltage v dd (v) 8 6 4 2 0 supply current i dd ( m a) 5.0 3.0 1.0 0.5 0.1 0.05 0.01 0.005 0.001 x1 x2 xt1 xt2 30 pf 330 k w 30 pf 18 pf 18 pf ceramic resonator 2.0 mhz crystal 32.768 khz 31 m pd75p068 x1 x2 f x (mhz) i dd (ma) (v dd = 5 v, ta = 25 ?c) 1.0 0.5 0 i dd (ma) (v dd = 3 v, ta = 25 ?c) x1 x2 40 30 20 10 0 v ol (v) i ol (ma) (ta = 25 ?c) 30 25 20 15 10 5 0 0 v ol (v) i ol (ma) (ta = 25 ?c) 12345 pcc = 0011 pcc = 0010 pcc = 0000 pcc = 0011 pcc = 0010 pcc = 0000 v dd = 2.7 v v dd = 3 v v dd = 5 v v dd = 6 v v dd = 2.7 v v dd = 3 v v dd = 4 v v dd = 5 v v dd = 6 v 3.0 2.5 2.0 1.5 1.0 0.5 0 0123456 main system clock halt mode main system clock halt mode f x (mhz) 0123456 i dd vs f x i dd vs f x 012345 v dd = 4 v i ol vs v ol (port 0) i ol vs v ol (ports 2 and 6) 32 m pd75p068 40 30 20 10 0 v ol (v) i ol (ma) (ta = 25 ?c) v dd = 2.7 v v dd = 3 v v dd = 4 v v dd = 6 v 012345 i ol vs v ol (port 3) v dd = 5 v 40 30 20 10 0 v ol (v) i ol (ma) (ta = 25 ?c) v dd = 2.7 v v dd = 3 v v dd = 5 v v dd = 6 v 012345 i ol vs v ol (ports 4 and 5) v dd = 4 v 15 10 5 0 v dd ?v oh (v) i oh (ma) (ta = 25 ?c) v dd = 2.7 v v dd = 3 v v dd = 4 v v dd = 6 v 012345 v dd = 5 v i oh vs v oh 33 m pd75p068 7. package drawings 42pin plastic shrink dip (600 mil) item millimeters inches a b c f g h i j k 39.13 max. 1.778 (t.p.) 3.2?.3 0.51 min. 4.31 max. 1.78 max. 0.17 15.24 (t.p.) 5.08 max. n 0.9 min. r 1.541 max. 0.070 max. 0.035 min. 0.126?.012 0.020 min. 0.170 max. 0.200 max. 0.600 (t.p.) 0.007 0.070 (t.p.) p42c-70-600a-1 a c d g notes 1) each lead centerline is located within 0.17 mm (0.007 inch) of its true position (t.p.) at maximum material condition. d 0.50?.10 0.020 m 0.25 0.010 +0.10 ?.05 0~15? 0~15? +0.004 ?.003 +0.004 ?.005 m k n l 13.2 0.520 2) item "k" to center of leads when formed parallel. 42 1 22 21 l m r b f h j i 34 m pd75p068 n a m f b 33 34 22 l 44 1 12 11 23 d c p detail of lead end s q 55 44 pin plastic qfp ( 10) g m i j h k p44gb-80-3b4-2 item millimeters inches a b c d f g h i j k l 13.6 0.4 10.0 0.2 1.0 0.35 0.10 0.15 10.0 0.2 0.535 0.039 0.039 0.006 0.031 (t.p.) 0.394 note m n 0.12 0.15 1.8 0.2 0.8 (t.p.) 0.005 0.006 +0.004 ?.003 each lead centerline is located within 0.15 mm (0.006 inch) of its true position (t.p.) at maximum material condition. 0.071 0.014 0.394 0.8 0.2 0.031 p 2.7 0.106 0.535 13.6 0.4 1.0 +0.009 ?.008 q 0.1 0.1 0.004 0.004 s 3.0 max. 0.119 max. +0.008 ?.009 +0.004 ?.005 +0.008 ?.009 +0.017 ?.016 +0.017 ?.016 +0.008 ?.009 +0.10 ?.05 35 m pd75p068 8. recommended soldering conditions the conditions listed below shall be met when soldering the m pd75p068. for details of the recommended soldering conditions, refer to our document "smd surface mount technology manual" (iei-1207) . please consult with our sales offices in case any other soldering process is used, or in case soldering is done under different conditions. table 8-1 soldering conditions for surface-mount devices m pd75p068gb-3b4: 44-pin plastic qfp (10 10 mm) caution do not apply more than a single process at once, except for partial heating method. table 8-2 soldering conditions for through hole mount devices m pd75p068cu: 42-pin plastic shrink dip (600 mil) caution in wave soldering, apply solder only to the lead section. care must be taken that jet solder does not come in contact with the main body of the package. soldering conditions peak packages surface temperature: 235 ?c reflow time: 30 seconds or less (at 210 ?c or more) maximum allowable number of reflow processes: 2 36 m pd75p068 appendix a development tools the following development tools are provided for developing systems including the m pd75p068: notes 1 . maintenance service only 2 . not contained in the ie-75001-r 3 . ms-dos versions 5.00 and 5.00a are provided with a task swap function. this function, however, cannot be used in these software. remark refer to 75x series selection guide (if-1027) for development tools manufactured by third parties. in-circuit emulator for the 75x series emulation board for the ie-75000-r and ie-75001-r emulation probe for the m pd75p068cu emulation probe for the m pd75p068gb. a 44-pin conversion socket, the ev-9200g-64, is attached to the probe. prom programmer prom programmer adapter for the m pd75p068cu/gb. connected to the pg-1500. ie-75000-r note 1 ie-75001-r ie-75000-r-em note 2 ep-75068cu-r ep-75068gb-r pg-1500 pa-75p008cu ev-9200g-44 ie control program pg-1500 controller ra75x relocatable assembler software host machine ? pc-9800 series (ms-dos tm ver. 3.30 to ver. 5.00a note 3 ) ? pc/at tm series (pc dos tm ver. 3.10) hardware 37 m pd75p068 appendix b related documents documents related to the device documents related to development tools other documents caution the above documents may be revised without notice. use the latest versions when you design an application system. document name ie-75000-r/ie-75001-r users manual ie-75000-r-em users manual ep-75068cu-r users manual ep-75068gb-r users manual pg-1500 users manual ra75x assembler package users manual pg-1500 controller users manual hardware software document name package manual smd surface mount technology manual quality grades on nec semiconductor devices nec semiconductor device reliability/quality control system electrostatic discharge (esd) test guide to quality assurance for semiconductor devices document name users manual application note (preliminary) 75x series selection guide document no. eeu-1455 eeu-1294 eeu-1317 eeu-1428 eeu-1335 eeu-1346 eeu-1363 eeu-1291 document no. document no. iei-1213 iei-1207 iei-1209 iei-1203 iei-1201 mei-1202 ieu-1366 iea-1296 if-1027 operation language 38 m pd75p068 [memo] 39 m pd75p068 cautions on cmos devices 1 countermeasures against static electricity for all moss caution when handling mos devices, take care so that they are not electrostatically charged. strong static electricity may cause dielectric breakdown in gates. when transporting or storing mos devices, use conductive trays, magazine cases, shock absorbers, or metal cases that nec uses for packaging and shipping. be sure to ground mos devices during assembling. do not allow mos devices to stand on plastic plates or do not touch pins. also handle boards on which mos devices are mounted in the same way. 2 cmos-specific handling of unused input pins caution hold cmos devices at a fixed input level. unlike bipolar or nmos devices, if a cmos device is operated with no input, an intermediate-level input may be caused by noise. this allows current to flow in the cmos device, resulting in a malfunction. use a pull-up or pull-down resistor to hold a fixed input level. since unused pins may function as output pins at unexpected times, each unused pin should be separately connected to the v dd or gnd pin through a resistor. if handling of unused pins is documented, follow the instructions in the document. 3 statuses of all mos devices at initialization caution the initial status of a mos device is unpredictable when power is turned on. since characteristics of a mos device are determined by the amount of ions implanted in molecules, the initial status cannot be determined in the manufacture process. nec has no responsibility for the output statuses of pins, input and output settings, and the contents of registers at power on. however, nec assures operation after reset and items for mode setting if they are defined. when you turn on a device having a reset function, be sure to reset the device first. m pd75p068 ms-dos is a trademark of microsoft corporation. pc/at and pc dos are trademarks of ibm corporation. [memo] no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. the devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. if customers intend to use nec devices for above applications or they intend to use standard quality grade nec devices for applications not intended by nec, please contact our sales people in advance. application examples recommended by nec corporation standard: computer, office equipment, communication equipment, test and measurement equipment, ma- chine tools, industrial robots, audio and visual equipment, other consumer products, etc. special: automotive and transportation equipment, traffic control systems, antidisaster systems, anticrime systems, etc. m4 92. 6 |
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